The present invention relates generally to MOSFET transistors and more generally to DMOS transistors having a trench structure.
DMOS (Double diffused MOS) transistors are a type of MOSFET (Metal On Semiconductor Field Effect Transistor) that use diffusion to form the transistor regions. DMOS transistors are typically employed as power transistors to provide high voltage circuits for power integrated circuit applications. DMOS transistors provide higher current per unit area when low forward voltage drops are required.
A typical discrete DMOS circuit includes two or more individual DMOS transistor cells which are fabricated in parallel. The individual DMOS transistor cells share a common drain contact (the substrate), while their sources are all shorted together with metal and their gates are shorted together by polysilicon. Thus, even though the discrete DMOS circuit is constructed from a matrix of smaller transistors, it behaves as if it were a single large transistor. For a discrete DMOS circuit it is desirable to maximize the conductivity per unit area when the transistor matrix is turned on by the gate.
One particular type of DMOS transistor is a so-called trench DMOS transistor in which the channel is formed vertically and the gate is formed in a trench extending between the source and drain. The trench, which is lined with a thin oxide layer and filled with polysilicon, allows less constricted current flow and thereby provides lower values of specific on-resistance. Examples of trench DMOS transistors are disclosed in U.S. Pat. Nos. 5,072,266, 5,541,425, and 5,866,931.
Electrostatic Discharge (ESD) presents a problem for semiconductor devices, particularly for DMOS structures. The high voltage transient signal from a static discharge can bias an object with more than 10,000 Volts. The unique hazard in DMOS devices is the high electric field that can develop across a relatively thin gate dielectric used in the normal course of operation of the device. The gate dielectric, which is often oxide, can rupture under high electric field conditions when the charge built up on the gate penetrates the gate oxide, which normally acts as an insulator. The effects of the permanent damage caused by the rupture may not be immediately apparent; therefore, the possibility of gate oxide rupture constitutes a realistic reliability concern. Because ESD conditions are common in many working environments, many commercial DMOS devices are equipped with self-contained ESD protection systems. These can be discrete or integrated with the main functional circuitry.
One method for protecting the gate of the devices from voltage above the oxide breakdown value employs a zener diode connected between the gate and source of the DMOS. An example of such a method and device is shown in U.S. Pat. No. 5,602,046. This technique improves the ESD rating of the MOSFET gate and helps avoid over-voltage damage.
One problem with the device shown in the previously mentioned patent is that its fabrication requires additional mask steps, increasing its complexity to manufacture and thus the cost of the device.
Accordingly, it would be desirable to provide a trench DMOS transistor having overvoltage protection from ESD which is relatively simple and inexpensive to manufacture.
The present invention provides a trench DMOS transistor having overvoltage protection. The transistor includes a substrate of a first conductivity type and a body region of a second conductivity type formed over the substrate. At least one trench extends through the body region and the substrate. An insulating layer lines the trench and overlies the body region. A conductive electrode is deposited in the trench so that it overlies the insulating layer. A source region of the first conductivity type is formed in the body region adjacent to the trench. An undoped polysilicon layer overlies a portion of the insulating layer. A plurality of cathode regions of the first conductivity type are formed in the undoped polysilicon layer. At least one anode region is in contact with adjacent ones of the plurality of cathode regions.
In accordance with one aspect of the invention, the undoped polysilicon layer overlies a portion of the insulating layer that is vertically displaced from the body region.
In accordance with another aspect of the invention, the plurality of cathode regions and the anode region are disposed in the portion of the insulating layer vertically displaced from the trench.
In accordance with yet another aspect of the invention, the plurality of cathode regions include boron implanted therein.
In accordance with another aspect of the invention the source region and the plurality of cathode regions are formed in simultaneous deposition steps.